Phase noise reduction by enhancing the filtering properties of a fully digital phase locked loop system
DOI:
https://doi.org/10.34169/2414-0651.2015.3(7).13-17Keywords:
comparative analysis of phase noise reduction, increase of filtering properties of the system of phase autoadjustment of frequency, connection of time jitter, spectral density of phase noise power, temporal instability of the oscillation period, digital system of phase auto-adjustment of frequencyAbstract
The comparative analysis of diminishing of phase noise and increase of fi lter properties of the system PLL is conducted in the article. Connection of temporal jitter is investigational with a spectral closeness powers of phase noise, which are needed for being of sentinel instability of period of vibrations fully of the system digital PLL.
Downloads
References
Системы фазовой автоподстройки частоты / В. В. Шахгильдян, А. А. Ляховкин; под ред. В. В. Шахгильдяна. – М.: Связь, 1972. – 220 с.
Kroupa V. Phase Lock Loops and Frequensy Synthesis. — Chichestes: John Wiley & Sons Ltd., 2003. DOI: https://doi.org/10.1002/0470014105
Комбинированная система фазовой автоподстройки частоты. В 3-х. Ч. 3. Показатели качества системы / Г. Ф. Зайцев, В. Л. Булгач, А. П. Полоневич, Н. В. Градобоева // Зв’язок. – 2012. – № 3. – С. 64–68.
Системы фазовой синхронизации с элементами дискретизации / Под ред. В. В. Шахгильдяна. – М. : Радио и связь, 1989.
Стеклов В. К. Анализ нелинейных систем фазовой автоподстройки / В. К. Стеклов, В. В. Мирошников // Радиотехника. – 2004. – № 138. – С. 105–110.
Lee B.-J. A 2.5-10Gb/s CMOS transceiver with alternating edge sampling phase detection for loop characteristic stabilization / Lee B-J et al // ISSCC Dig. Tech. Papers, 2003, No. 2, pp. 76–77.
Fast Frequency Acquisition Phase-Frequency Detectors for GSa/s Phase-Locked Loops / А. П. Бондарєв et al. // EEE J. Solid-State Circuits, 2002, Vol. 37, No. 10, pp. 1331–1334. DOI: https://doi.org/10.1109/JSSC.2002.803048
Nash G. Phase-Locked Loop Design / G. Nash // Fundamentals Document Number: AN535 Rev. 1.0. – 02/2006.
Mansuri M. A low-power lovv-jitter adaptive bandwidth PLL and clock buffer / Mansuri M. and Yang. C.-K. // ISSCC Dig. Tech. Papers, 2009, No 2, pp. 430–431. DOI: https://doi.org/10.1109/ISSCC.2003.1234370
A low-power multiplying DLL for lovv-jitter multigigahertz clock generation in highly integrated digital chips / Farjad-Rad R. et al. // IEEE J. of Solid StateCircuits, 2002, Vol. 37, No 12, pp. 1804–1812. DOI: https://doi.org/10.1109/JSSC.2002.804340
Downloads
Published
How to Cite
Issue
Section
